Gray  = Original 6502 instruction
Blue  = New for 65C02
Green = New for HuC6280
Red   = Illegal instruction (NOP on 65C02/HuC6280, undefined on 6502)

Instructions:

Token	Flags		Name

ADC 	NV0---ZC	add with carry
AND 	N-0---Z-	logical AND
ASL 	N-0---ZC	arithmetic shift left
BCC 	--0-----	branch on carry clear
BCS 	--0-----	branch on carry set
BEQ 	--0-----	branch on equal
BIT 	NV0---Z-	bit test
BMI 	--0-----	branch on minus
BNE 	--0-----	branch on not equal
BPL 	--0-----	branch on plus
BRK 	--0-----	break
BVC 	--0-----	branch on overflow clear
BVS 	--0-----	branch on overflow set
CLC 	--0-----	clear carry flag
CLD 	--0-----	clear decimal mode flag
CLI 	--0-----	clear interrupt enable flag
CLV 	--0-----	clear overflow flag
CMP 	N-0---ZC	compare to accumulator
CPX 	N-0---ZC	compare to X index
CPY 	N-0---ZC	compare to Y index
DEC 	N-0---Z-	decrement
DEX 	N-0---Z-	decrement X index
DEY 	N-0---Z-	decrement Y index
EOR 	N-0---Z-	logical exclusive OR
INC 	N-0---Z-	increment
INX 	N-0---Z-	increment X index
INY 	N-0---Z-	increment Y index
JMP 	--0-----	jump
JSR 	--0-----	jump to subroutine
LDA 	N-0---Z-	load accumulator
LDX 	N-0---Z-	load X index
LDY 	N-0---Z-	load Y index
LSR 	0-0---ZC	logical shift right
NOP 	--0-----	no operation
ORA 	N-0---Z-	logical OR accumulator
PHA 	--0-----	push accumulator
PHP 	--0-----	push processor status flags
PLA 	N-0---Z-	pull accumulator
PLP 	NVTBDIZC	pull processor status flags
ROL 	N-0---ZC	rotate left
ROR 	N-0---ZC	rotate right
RTI 	NVTBDIZC	return from interrupt
RTS 	--0-----	return from subroutine
SBC 	NV0---ZC	subtract with carry
SEC 	--0----1	set carry flag
SED 	--0-1---	set decimal flag
SEI 	--0--1--	set interrupt enable flag
STA 	--0-----	store accumulator
STX 	--0-----	store X index
STY 	--0-----	store Y index
TAX 	N-0---Z-	transfer accumulator to X index
TAY 	N-0---Z-	transfer accumulator to Y index
TSX 	N-0---Z-	transfer stack pointer to X index
TXA 	N-0---Z-	transfer X index to accumulator
TXS 	--0-----	transfer X index to stack pointer
TYA 	N-0---Z-	transfer Y index to accumulator
ILL 	--0-----	illegal instruction
BRA 	--0-----	branch
STZ 	--0-----	store zero
TRB 	NV0---Z-	test and reset bits
TSB 	NV0---Z-	test and set bits
DEA 	N-0---Z-	decrement accumulator
INA 	N-0---Z-	increment accumulator
SAX 	--0-----	swap accumulator and X index
BSR 	--0-----	branch to subroutine
PHX 	--0-----	push X index
PHY 	--0-----	push Y index
PLX 	N-0---Z-	pull X index
PLY 	N-0---Z-	pull Y index
CSH 	--0-----	change speed high
CSL 	--0-----	change speed low
TAM 	--0-----	transfer accumulator to MPR register
TMA 	--0-----	transfer MPR register to accumulator
CLA 	--0-----	clear accumulator
CLY 	--0-----	clear Y index
CLX 	--0-----	clear X index
ST0 	--0-----	store to VDC address zero
ST1 	--0-----	store to VDC address two
ST2 	--0-----	store to VDC address three
TST 	NV0---Z-	test
SET 	--1-----	set T flag
TDD 	--0-----	transfer decrement decrement
TIA 	--0-----	transfer increment alternate
TII 	--0-----	transfer increment increment
TIN 	--0-----	transfer increment none
TAI 	--0-----	transfer alternate increment
SAY 	--0-----	swap accumulator and Y index
SXY 	--0-----	swap X index and Y index
SMB0	--0-----	set memory bit 0
SMB1	--0-----	set memory bit 1
SMB2	--0-----	set memory bit 2
SMB3	--0-----	set memory bit 3
SMB4	--0-----	set memory bit 4
SMB5	--0-----	set memory bit 5
SMB6	--0-----	set memory bit 6
SMB7	--0-----	set memory bit 7
RMB0	--0-----	reset memory bit 0
RMB1	--0-----	reset memory bit 1
RMB2	--0-----	reset memory bit 2
RMB3	--0-----	reset memory bit 3
RMB4	--0-----	reset memory bit 4
RMB5	--0-----	reset memory bit 5
RMB6	--0-----	reset memory bit 6
RMB7	--0-----	reset memory bit 7
BBS0	--0-----	branch on memory bit 0 set
BBS1	--0-----	branch on memory bit 1 set
BBS2	--0-----	branch on memory bit 2 set
BBS3	--0-----	branch on memory bit 3 set
BBS4	--0-----	branch on memory bit 4 set
BBS5	--0-----	branch on memory bit 5 set
BBS6	--0-----	branch on memory bit 6 set
BBS7	--0-----	branch on memory bit 7 set
BBR0	--0-----	branch on memory bit 0 reset
BBR1	--0-----	branch on memory bit 1 reset
BBR2	--0-----	branch on memory bit 2 reset
BBR3	--0-----	branch on memory bit 3 reset
BBR4	--0-----	branch on memory bit 4 reset
BBR5	--0-----	branch on memory bit 5 reset
BBR6	--0-----	branch on memory bit 6 reset
BBR7	--0-----	branch on memory bit 7 reset

Addressing modes:

Token	Name				Syntax

ACC 	accumulator                   	a
IMP 	implied                       	
IMM 	immediate                     	#$nn
ABS 	absolute                      	$nnnn
ZPG 	zero page                     	<$nn
ZPX 	zero page, x-indexed          	<$nn,x
ZPY 	zero page, y-indexed          	<$nn,y
ZPI 	zero page indirect            	[$nn]
ABX 	absolute x-indexed            	$nnnn,x
ABY 	absolute y-indexed            	$nnnn,y
REL 	relative offset               	*
IDX 	zero page pre-indexed         	[$nn,x]
IDY 	zero page post-indexed        	[$nn],y
IND 	indirect                      	[$nnnn]
IAX 	indirect, x-indexed           	[$nnnn,x]
BLK 	block transfer                	$nnnn,$nnnn,$nnnn
ZRL 	zero page, relative offset    	<$nn, *
IMZ 	immediate zero page           	#$nn,<$nn
IZX 	immediate zero page, x-indexed	#$nn,<$nn,x
IMA 	immediate absolute            	#$nn,<$nnnn
IMX 	immediate absolute, x-indexed 	#$nn,<$nnnn,x

Instruction list with cycles and syntax:

Opcode	Cycles	Instruction

$00	8	BRK  
$01	7	ORA  [$nn,x]
$02	3	SXY  
$03	4	ST0  #$nn
$04	6	TSB  <$nn
$05	4	ORA  <$nn
$06	2	ASL  <$nn
$07	7	RMB0 <$nn
$08	3	PHP  
$09	2	ORA  #$nn
$0A	1	ASL  a
$0B	2	ILL  
$0C	7	TSB  $nnnn
$0D	5	ORA  $nnnn
$0E	3	ASL  $nnnn
$0F	6	BBR0 <$nn, *
$10	2	BPL  *
$11	7	ORA  [$nn],y
$12	7	ORA  [$nn]
$13	4	ST1  #$nn
$14	6	TRB  <$nn
$15	4	ORA  <$nn,x
$16	2	ASL  <$nn,x
$17	7	RMB1 <$nn
$18	2	CLC  
$19	5	ORA  $nnnn,y
$1A	2	INA  a
$1B	2	ILL  
$1C	7	TRB  $nnnn
$1D	5	ORA  $nnnn,x
$1E	3	ASL  $nnnn,x
$1F	6	BBR1 <$nn, *
$20	7	JSR  $nnnn
$21	7	AND  [$nn,x]
$22	3	SAX  
$23	4	ST2  #$nn
$24	4	BIT  <$nn
$25	4	AND  <$nn
$26	6	ROL  <$nn
$27	7	RMB2 <$nn
$28	4	PLP  
$29	2	AND  #$nn
$2A	2	ROL  a
$2B	2	ILL  
$2C	5	BIT  $nnnn
$2D	5	AND  $nnnn
$2E	7	ROL  $nnnn
$2F	6	BBR2 <$nn, *
$30	2	BMI  *
$31	7	AND  [$nn],y
$32	7	AND  [$nn]
$33	2	ILL  
$34	4	BIT  <$nn,x
$35	4	AND  <$nn,x
$36	6	ROL  <$nn,x
$37	7	RMB3 <$nn
$38	2	SEC  
$39	5	AND  $nnnn,y
$3A	2	DEA  a
$3B	2	ILL  
$3C	5	BIT  $nnnn,x
$3D	5	AND  $nnnn,x
$3E	7	ROL  $nnnn,x
$3F	6	BBR3 <$nn, *
$40	7	RTI  
$41	7	EOR  [$nn,x]
$42	3	SAY  
$43	4	TMA  #$nn
$44	8	BSR  *
$45	4	EOR  <$nn
$46	6	LSR  <$nn
$47	7	RMB4 <$nn
$48	3	PHA  
$49	2	EOR  #$nn
$4A	2	LSR  a
$4B	2	ILL  
$4C	4	JMP  $nnnn
$4D	5	EOR  $nnnn
$4E	7	LSR  $nnnn
$4F	6	BBR4 <$nn, *
$50	2	BVC  *
$51	7	EOR  [$nn],y
$52	7	EOR  [$nn]
$53	5	TAM  #$nn
$54	3	CSL  
$55	4	EOR  <$nn,x
$56	6	LSR  <$nn,x
$57	7	RMB5 <$nn
$58	2	CLI  
$59	5	EOR  $nnnn,y
$5A	3	PHY  
$5B	2	ILL  
$5C	2	ILL  
$5D	5	EOR  $nnnn,x
$5E	7	LSR  $nnnn,x
$5F	6	BBR5 <$nn, *
$60	7	RTS  
$61	7	ADC  [$nn,x]
$62	2	CLA  
$63	2	ILL  
$64	4	STZ  <$nn
$65	4	ADC  <$nn
$66	6	ROR  <$nn
$67	7	RMB6 <$nn
$68	4	PLA  
$69	2	ADC  #$nn
$6A	2	ROR  a
$6B	2	ILL  
$6C	7	JMP  [$nnnn]
$6D	5	ADC  $nnnn
$6E	7	ROR  $nnnn
$6F	6	BBR6 <$nn, *
$70	2	BVS  *
$71	7	ADC  [$nn],y
$72	7	ADC  [$nn]
$73	17	TII  $nnnn,$nnnn,$nnnn
$74	4	STZ  <$nn,x
$75	4	ADC  <$nn,x
$76	6	ROR  <$nn,x
$77	7	RMB7 <$nn
$78	2	SEI  
$79	5	ADC  $nnnn,y
$7A	4	PLY  
$7B	2	ILL  
$7C	7	JMP  [$nnnn,x]
$7D	5	ADC  $nnnn,x
$7E	7	ROR  $nnnn,x
$7F	6	BBR7 <$nn, *
$80	4	BRA  *
$81	7	STA  [$nn,x]
$82	2	CLX  
$83	7	TST  #$nn,<$nn
$84	4	STY  <$nn
$85	4	STA  <$nn
$86	4	STX  <$nn
$87	7	SMB0 <$nn
$88	2	DEY  
$89	2	BIT  #$nn
$8A	2	TXA  
$8B	2	ILL  
$8C	5	STY  $nnnn
$8D	5	STA  $nnnn
$8E	5	STX  $nnnn
$8F	6	BBS0 <$nn, *
$90	2	BCC  *
$91	7	STA  [$nn],y
$92	7	STA  [$nn]
$93	8	TST  #$nn,<$nn,x
$94	4	STY  <$nn,x
$95	4	STA  <$nn,x
$96	4	STX  <$nn,y
$97	7	SMB1 <$nn
$98	2	TYA  
$99	5	STA  $nnnn,y
$9A	2	TXS  
$9B	2	ILL  
$9C	5	STZ  $nnnn
$9D	5	STA  $nnnn,x
$9E	5	STZ  $nnnn,x
$9F	6	BBS1 <$nn, *
$A0	2	LDY  #$nn
$A1	7	LDA  [$nn,x]
$A2	2	LDX  #$nn
$A3	7	TST  #$nn,<$nnnn
$A4	4	LDY  <$nn
$A5	4	LDA  <$nn
$A6	4	LDX  <$nn
$A7	7	SMB2 <$nn
$A8	2	TAY  
$A9	2	LDA  #$nn
$AA	2	TAX  
$AB	2	ILL  
$AC	5	LDY  $nnnn
$AD	5	LDA  $nnnn
$AE	5	LDX  $nnnn
$AF	6	BBS2 <$nn, *
$B0	2	BCS  *
$B1	7	LDA  [$nn],y
$B2	7	LDA  [$nn]
$B3	8	TST  #$nn,<$nnnn,x
$B4	4	LDY  <$nn,x
$B5	4	LDA  <$nn,x
$B6	4	LDX  <$nn,y
$B7	7	SMB3 <$nn
$B8	2	CLV  
$B9	5	LDA  $nnnn,y
$BA	2	TSX  
$BB	2	ILL  
$BC	5	LDY  $nnnn,x
$BD	5	LDA  $nnnn,x
$BE	5	LDX  $nnnn,y
$BF	6	BBS3 <$nn, *
$C0	2	CPY  #$nn
$C1	7	CMP  [$nn,x]
$C2	2	CLY  
$C3	17	TDD  $nnnn,$nnnn,$nnnn
$C4	4	CPY  <$nn
$C5	4	CMP  <$nn
$C6	6	DEC  <$nn
$C7	7	SMB4 <$nn
$C8	2	INY  
$C9	2	CMP  #$nn
$CA	2	DEX  
$CB	2	ILL  
$CC	5	CPY  $nnnn
$CD	5	CMP  $nnnn
$CE	7	DEC  $nnnn
$CF	6	BBS4 <$nn, *
$D0	2	BNE  *
$D1	7	CMP  [$nn],y
$D2	7	CMP  [$nn]
$D3	17	TIN  $nnnn,$nnnn,$nnnn
$D4	3	CSH  
$D5	4	CMP  <$nn,x
$D6	6	DEC  <$nn,x
$D7	7	SMB5 <$nn
$D8	2	CLD  
$D9	5	CMP  $nnnn,y
$DA	3	PHX  
$DB	2	ILL  
$DC	2	ILL  
$DD	5	CMP  $nnnn,x
$DE	7	DEC  $nnnn,x
$DF	6	BBS5 <$nn, *
$E0	2	CPX  #$nn
$E1	7	SBC  [$nn,x]
$E2	2	ILL  
$E3	17	TIA  $nnnn,$nnnn,$nnnn
$E4	4	CPX  <$nn
$E5	4	SBC  <$nn
$E6	6	INC  <$nn
$E7	7	SMB6 <$nn
$E8	2	INX  
$E9	2	SBC  #$nn
$EA	2	NOP  
$EB	2	ILL  
$EC	5	CPX  $nnnn
$ED	5	SBC  $nnnn
$EE	7	INC  $nnnn
$EF	6	BBS6 <$nn, *
$F0	2	BEQ  *
$F1	7	SBC  [$nn],y
$F2	7	SBC  [$nn]
$F3	17	TAI  $nnnn,$nnnn,$nnnn
$F4	2	SET  
$F5	4	SBC  <$nn,x
$F6	6	INC  <$nn,x
$F7	7	SMB7 <$nn
$F8	2	SED  
$F9	5	SBC  $nnnn,y
$FA	4	PLX  
$FB	2	ILL  
$FC	2	ILL  
$FD	5	SBC  $nnnn,x
$FE	7	INC  $nnnn,x
$FF	6	BBS7 <$nn, *